Guangzhou Eric Wei Chemical Co., Ltd.
Guangzhou Eric Wei Chemical Co., Ltd.

3-Inch CdSe Single Crystal Substrate

II-VI Incorporated CdSe Single Crystal Substrate Series 3-Inch CdSe substrate features high-purity (99.999%), low-dislocation-density single-crystal cadmium selenide wafers ideal for optoelectronic device epitaxy, IR detectors, and nonlinear optics applications requiring excellent thermal stability and uniform crystal structure.
  • 3 inch cdse single crystal substrate_7a978326
  • 3 inch cdse single crystal substrate_7a978326

Features Of 3-Inch CdSe Single Crystal Substrate

  1. High-purity single-crystal structure with low dislocation density (< 1 × 10⁴ cm⁻²) for superior optoelectronic performance.

  2. Uniform 3-inch (76.2 mm) diameter and ±0.1 mm thickness tolerance, enabling high-yield wafer-level device fabrication.

  3. Chemically stable (0001) basal plane surface, polished to epi-ready finish (Ra < 0.2 nm) with optional Se- or Cd-termination control.

  4. Wide direct bandgap (~1.74 eV at 300 K) ideal for visible-light photodetectors, lasers, and nonlinear optical devices.

  5. Thermally robust up to 720 °C in inert atmosphere, supporting high-temperature MBE and MOCVD epitaxial growth.

Typical Applications Of 3-Inch CdSe Single Crystal Substrate

  1. Heteroepitaxial growth of II–VI quantum wells and superlattices for tunable visible-light emitters.

  2. Substrate for high-resolution X-ray and electron beam lithography mask blanks in nanofabrication.

  3. Platform for fundamental studies of excitonic physics, valley polarization, and 2D van der Waals heterostructures.

  4. Base material for radiation-hardened photodetectors in space-based optical sensing systems.

  5. Template for seeded crystal growth of CdSe-based nanowires and core–shell nanostructures.

Specifications Of 3-Inch CdSe Single Crystal Substrate



Chemical TypeCadmium Selenide (CdSe), ultra-high purity (99.999% min)
Product FormSingle-crystal wafer, hexagonal wurtzite structure
Orientation(0001) C-plane, ±0.5° off-axis option available
Diameter76.2 mm (3.0 inch) ±0.1 mm
Thickness500 µm ±25 µm (standard); custom thicknesses 350–1000 µm available
Surface FinishDouble-side polished; front side epi-ready (Ra < 0.2 nm), back side ground
Primary ApplicationsEpitaxial template, optoelectronic research substrate, calibration standard
Regulatory ComplianceRoHS-compliant; REACH SVHC screening performed; SDS available upon request


Compatible Systems Of 3-Inch CdSe Single Crystal Substrate

Common Compatible SystemsSuitability
Veeco GEN10 MBE SystemHighly Recommended – Optimized for CdSe thermal stability and Se-flux control
IQE MOCVD Reactor (e.g., CCS-3x2)Recommended – Compatible with H₂Se and DMCD precursors under standard CdSe growth conditions
JEOL JSM-7900F SEM/EBSD PlatformHighly Recommended – Low charging, high crystallographic contrast for orientation mapping
Keysight B1500A Semiconductor Parameter AnalyzerSuitable – Supports contact probe testing with standard 3-inch wafer chuck and guard ring configuration

3-Inch CdSe Single Crystal Substrate – Frequently Asked Questions (FAQ)

Q1: What is the CAS Number for CdSe?

A: The CAS Registry Number for cadmium selenide is 1306-23-6.


Q2: Is this substrate suitable for aqueous processing or wet chemical etching?

A: No — CdSe is susceptible to oxidation and dissolution in acidic or oxidizing aqueous environments. Processing requires inert atmosphere, anhydrous solvents, or plasma-based dry etching only.


Q3: How does this CdSe substrate compare to GaAs or Si in terms of lattice matching for epitaxy?

A: CdSe has a lattice constant of a = 4.30 Å, c = 7.01 Å (wurtzite), offering better match to other II–VI compounds (e.g., ZnSe, CdTe) than to III–V or elemental semiconductors. It is not lattice-matched to GaAs (a = 5.65 Å) or Si (a = 5.43 Å), requiring buffer layers or strain-engineered templates.


Q4: Does this product comply with EU SCIP database requirements for articles containing SVHCs?

A: Yes — as a homogeneous material containing cadmium (SVHC candidate), full SCIP submission documentation is provided with commercial orders per Article 9 of EU REACH Regulation (EC) No 1907/2006.


Q5: Can Cd or Se leach into adjacent thin films during high-temperature annealing?

A: Minimal interdiffusion occurs below 550 °C in sealed UHV or high-purity N₂ environments. For temperatures > 550 °C, diffusion barriers (e.g., thin ZnS or AlN capping layers) are recommended to suppress elemental migration.



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